Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning-Reference-Cited by-同舟云学术

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

Published:2008-03-03 Issue:9 Volume:92 Page:092901
ISSN:0003-6951
Container-title:Applied Physics Letters
language:en
Short-container-title:Appl. Phys. Lett.

Author:

Kirsch P. D.,Sivasubramani P.,Huang J.,Young C. D.,Quevedo-Lopez M. A.,Wen H. C.,Alshareef H.,Choi K.,Park C. S.,Freeman K.,Hussain M. M.,Bersuker G.,Harris H. R.,Majhi P.,Choi R.,Lysaght P.,Lee B. H.,Tseng H.-H.,Jammy R.,Böscke T. S.,Lichtenwalner D. J.,Jur J. S.,Kingon A. I.

Publisher

AIP Publishing

Subject

Physics and Astronomy (miscellaneous)

Link

http://aip.scitation.org/doi/pdf/10.1063/1.2890056

Reference18 articles.

1. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

2. Ultrascaled hafnium silicon oxynitride gate dielectrics with excellent carrier mobility and reliability

3. Determination of free carrier density and space charge layer variation in nanocrystalline In3+ doped tin oxides using Fourier transforminfrared spectroscopy

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