Generation and relaxation phenomena of positive charge and interface trap in a metal‐oxide‐semiconductor structure
Author:
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.359445
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1. Model for Charge Accumulation in n- and p-MOS Transistors during Tunneling Electron Injection from a Gate;Semiconductors;2018-05-15
2. Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology;Microelectronics Reliability;2002-12
3. Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectrics for advanced complementary metal–oxide–semiconductor technology;Applied Physics Letters;2001-11-19
4. OXIDE WEAROUT, BREAKDOWN, AND RELIABILITY;International Journal of High Speed Electronics and Systems;2001-09
5. Hole trapping and trap generation in the gate silicon dioxide;IEEE Transactions on Electron Devices;2001-06
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