The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0

Author:

Waterman Andrew,Lee Yunsup,Patterson David A.,Asanovi Krste

Publisher

Defense Technical Information Center

Cited by 110 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. UVM Verification of RISC-V Instruction set;2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC);2024-06-28

2. Evaluating Trusted Firmware Remote Attestation on ARM and RISC-V Edge Computing Prototypes;2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST);2024-06-26

3. A multimode SHA-3 accelerator based on RISC-V system;IEICE Electronics Express;2024-06-10

4. 500 MHz CMOS 28-nm Floating Point Arithmetic Unit for 32-Bit RISC-V Microprocessors;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

5. Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

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