500 MHz CMOS 28-nm Floating Point Arithmetic Unit for 32-Bit RISC-V Microprocessors
Author:
Affiliation:
1. University of Milano-Bicocca,Department of Physics,Milan,Italy
2. University of Milano-Bicocca,Department of Informatics, Systems and Communication,Milan,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10559643/10559661/10559675.pdf?arnumber=10559675
Reference8 articles.
1. Ieee standard for floating-point arithmetic,2019
2. The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
3. Some schemes for parallel multipliers;Dadda;Alta frequenza,1965
4. A comparison of dadda and wallace multiplier delays;Whitney;Advanced signal processing algorithms, architectures, and implementations XIII,2003
5. Implementation of Efficient Digit Recurrence Class of Division Algorithms
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