Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs

Author:

Ito Yasuaki1,Nakano Koji1

Affiliation:

1. Hiroshima University

Publisher

IJNC Editorial Committee

Reference15 articles.

1. [1] FengWei An and Koji Nakano. An architecture for veryfing collatz conjecture using an FPGA. In Proc. of the International Conference on Applications and Principles of Informatin Science, pages 375–378, 2009.

2. [2] J. L. Bordim, Y. Ito, and K. Nakano. Accelerating the CKY parsing using FPGAs. IEICE Transactions on Information and Systems, E86-D(5):803–810, May 2003.

3. [3] J. L. Bordim, Y. Ito, and K. Nakano. Instance-specific solutions to accelerate the CKY parsing for large context-free grammars. International Journal on Foundations of Computer Science, pages 403–416, 2004.

4. [4] Tomás Oliveira e Silva. Maximum excursion and stopping time record-holders for the 3x + 1 problem: Computational results. Mathematics of Computation, 68(225):371–384, Jan 1999. Up to date computational results can be found at http://www.ieeta.pt/~tos/3x+1.html.

5. [5] Shuichi Ichikawa and Naohiro Kobayashi. Preliminary study of custom computing hardware for the 3x+1 problem. In Proc. of IEEE TENCON 2004, pages 387–390, 2004.

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