Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing

Author:

Yoshimura Chihiro1,Hayashi Masato1,Okuyama Takuya1,Yamaoka Masanao1

Affiliation:

1. Hitachi, Ltd.

Publisher

IJNC Editorial Committee

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems;IEEE Nanotechnology Magazine;2024-06

3. An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization Model;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

4. Hybrid Optimization Method Using Simulated-Annealing-Based Ising Machine and Quantum Annealer;Journal of the Physical Society of Japan;2023-12-15

5. A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

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