VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems-Reference-Cited by-同舟云学术

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VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems

Published:2024-06 Issue:3 Volume:18 Page:23-30
ISSN:1932-4510
Container-title:IEEE Nanotechnology Magazine
language:
Short-container-title:IEEE Nanotechnology Mag.

Author:

Chen Yuan-Ho¹^ORCID,Hua Hsin-Tung¹,Nien Chin-Fu²^ORCID,Lin Shinn-Yn³^ORCID

Affiliation:

1. Department of Electronics Engineering, Chang Gung University, Taoyuan City, Taiwan

2. Department of Computer Science and Information Engineering, Chang Gung University, Taoyuan City, Taiwan

3. Department of Radiation Oncology, Chang Gung Memorial Hospital, Chang Gung University, Taoyuan City, Taiwan

Funder

National Science and Technology Council

Chang Gung University

Chang Gung Memorial Hospital

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4451717/10531090/10504927.pdf?arnumber=10504927

Reference32 articles.

1. A Hybrid Approach for Solving Optimization Problems on Small Quantum Computers

2. Algorithms for quantum computation: discrete logarithms and factoring

3. Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins

4. Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs

5. A 2 $\times$ 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

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