Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems-Reference-Cited by-同舟云学术

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Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems

Published:2024-09 Issue:9 Volume:71 Page:4291-4295
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chen Yuan-Ho¹^ORCID,Chou Che-An¹,Nien Chin-Fu²^ORCID,Lin Shinn-Yn¹^ORCID

Affiliation:

1. Department of Electronics Engineering, Chang Gung University, Taoyuan, Taiwan

2. Department of Computer Science and Information Engineering, Chang Gung University, Taoyuan, Taiwan

Funder

National Science and Technology Council of Taiwan

Chang Gung Memorial Hospital

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10666887/10478118.pdf?arnumber=10478118

Reference19 articles.

1. A grasp-knapsack hybrid for a nurse-scheduling problem

2. A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

3. 2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

4. CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem

5. A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems

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