Author:
Mil’shtein Samson,Devarakonda Lalitha,Zanchi Brian,Palma John
Abstract
Abstract
The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V
g1 > V
g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.
Publisher
Springer Science and Business Media LLC
Subject
Condensed Matter Physics,General Materials Science
Reference10 articles.
1. Hisamoto D, Lee W, Kedzierski J, Takeuchi H, Asano K, Kuo C, Anderson E, King T, Bokor J, Chenming H: FinFET - a self-aligned double-gate MOSFET scalable to 20 nm. IEEE T Electron Dev 2000, 47: 12.
2. Choi YJ, Choi BY, Kim KR, Lee JD, Park B-G: A new 50 nm n-MOSFET with side-gates for virtual source-drain extensions. IEEE T Electron Dev 2002, 49: 1833–1835. 10.1109/TED.2002.803648
3. Han S, Si C, Lee J, Shin H: 50 nm MOSFET with electrical induced source/drain (S/D) extensions. IEEE T Electron Dev 2001, 48: 2058–2064. 10.1109/16.944196
4. Ersland P, Somisettya S, Gila C, Mil’shtein S: p-HEMT with tailored field. Microelectron J 2003, 34: 359–361. 10.1016/S0026-2692(03)00146-0
5. Wong H-SP, Chan KK, Taur Y: Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. In Technical Digest. International: Dec 7–10 1997;Washington DC. New York: IEEE; 1997:427–430.
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献