SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects
Author:
Affiliation:
1. Acharya Nagarjuna University, Department of ECE, Nagarjuna Nagar, Guntur, India
2. DMSSSVH College of Engineering, Department of ECE, India
3. Department of ECE, GITAM University, Visakhapatnam, India
Publisher
Institute of Physics, Polish Academy of Sciences
Subject
General Physics and Astronomy
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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3. Optimisation of SRAM cell in 7-nm node by response surface method;International Journal of Electronics;2021-09-05
4. SS < 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications;Materials Today: Proceedings;2020-11
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