1. Calin, T., Nicolaidis, M., and Velazco, R., Upset hardened memory design for submicron CMOS technology, IEEE Trans. Nucl. Sci. 1996, vol. 43, no. 6, pp. 2874–2878.
2. Massengill, L.W., Bhuva, B.L., Holman, W.T., Alles, M.L., and Loveless, T.D., Technology scaling and soft error reliability, in Proceedings of IEEE International Reliability Physics Symposium, 2012, pp. 3C.1.1–3C1.7.
3. Loveless, T.D., Jagannathan, S., Reece, T., Chetia, J., Bhuva, B.L., McCurdy, M.W., Massengill, L.W., Wen, S.-J., Wong, R., and Rennie, D., Neutronand proton-induced single event upsets for Dand DICE-flip/flop designs at a 40 nm technology node, IEEE Trans. Nucl. Sci. 2011, vol. 58, no. 3, pp. 1008–1014.
4. Seifert, N.P., Ambrose, V., Gill, B., Shi, Q., Allmon, R., Recchia, C., Mukherjee, S., Nassif, N., Krause, J., Pickholtz, J., and Balasubramanian, A., On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies, in Proceedings of IEEE International Reliability Physics Symposium 2010, pp. 188–197.
5. Baze, M.P., Hughlock, B., Wert, J., Tostenrude, J., Massengill, L., Amusan, O., Lacoe, R., Lilja, K., and Johnson, M., Angular dependence of single-event sensitivity in hardened flip/flop design, IEEE Trans. Nucl. Sci. 2008, vol. 55, no. 6, pp. 3295–3301.