Author:
Kim Taikyu,Choi Cheol Hee,Byeon Pilgyu,Lee Miso,Song Aeran,Chung Kwun-Bum,Han Seungwu,Chung Sung-Yoon,Park Kwon-Shik,Jeong Jae Kyeong
Abstract
AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.
Funder
LG Display
National Research Foundation of Korea
Publisher
Springer Science and Business Media LLC
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science,General Chemistry
Cited by
45 articles.
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