Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure
Author:
Affiliation:
1. Department of Electronics and Communication, GIET University, Gunupur, Odisha, India
2. Department of ECE, GVP College of engineering (A), Visakhapatnam, Andhra Pradesh, India
Abstract
Publisher
FOREX Publication
Subject
Electrical and Electronic Engineering,Engineering (miscellaneous)
Reference24 articles.
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2. Goel, S., Kumar, A., and Bayoumi, M. Design of robust, energy-efficient full adders for deep- submicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006; 14(12): 1309-21. doi/10.1109/TVLSI.2006.887807
3. Aguirre-Hernandez, M., and Linares-Aranda, M. CMOS full-adders for energy-efficient arithmetic applications. IEEE transactions on very large scale integration (VLSI) systems. 2011; 19(4):718-21. doi: 10.1109/TVLSI.2009.2038166
4. Foroutan, V., Taheri, M., Navi, K., and Mazreah, A. A. Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integration. 2014; 47(1):48-61. doi.org/10.1016/j.vlsi.2013.05.001
5. Hassoune, I., Flandre, D., O’Connor, I., and Legat, J.D. ULPFA: A new efficient design of a power-aware full adder. IEEE Transactions on Circuits and Systems. I, Reg. Papers. 2010; 57(8):2066-74. doi:10.1109/TCSI.2008.2001367
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