Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Author:

Foroutan Vahid,Taheri MohammadReza,Navi Keivan,Mazreah Arash Azizi

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference30 articles.

1. Two new low-power full adders based on majority-not gates;Navi,2009

2. Novel direct designs for 3-input XOR function for low power and high-speed applications;Moaiyeri;International Journal of Electronics (Taylor and Francis),2010

3. A novel low power full-adder cell for low voltage;Navi;Integration the VLSI Journal (Elsevier),2009

4. Analysis and comparison of the full adder block;Alioto;IEEE Transactions on VLSI,2002

5. R. Shalem, E. John, L.K. John, A novel low-power energy recovery full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, February 1999, pp. 380–383.

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