Gate-Tunable Tunneling Transistor Based on a Thin Black Phosphorus–SnSe2 Heterostructure-Reference-Cited by-同舟云学术

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Gate-Tunable Tunneling Transistor Based on a Thin Black Phosphorus–SnSe2 Heterostructure

Published:2019-05-30 Issue:23 Volume:11 Page:20973-20978
ISSN:1944-8244
Container-title:ACS Applied Materials & Interfaces
language:en
Short-container-title:ACS Appl. Mater. Interfaces

Author:

Na Junhong¹²^ORCID,Kim Youngwook¹,Smet Jurgen H.¹^ORCID,Burghard Marko¹,Kern Klaus¹³

Affiliation:

1. Max Planck Institute for Solid State Research, Heisenbergstrasse 1, D-70569 Stuttgart, Germany

2. Department of Energy Science, Sungkyunkwan University, 16419 Suwon, Republic of Korea

3. Institut de Physique, École Polytechnique Fédérale de Lausanne, CH-1015 Lausanne, Switzerland

Funder

European Commission

National Research Foundation of Korea

Alexander von Humboldt-Stiftung

Publisher

American Chemical Society (ACS)

Subject

General Materials Science

Link

http://pubs.acs.org/doi/pdf/10.1021/acsami.9b02589

Reference45 articles.

1. Tunnel field-effect transistors as energy-efficient electronic switches

2. A review of selected topics in physics based modeling for tunnel field-effect transistors

3. Low-Voltage Tunnel Transistors for Beyond CMOS Logic

4. Moselund, K. E.; Ghoneim, H.; Bjork, M. T.; Schmid, H.; Karg, S.; Lortscher, E.; Riess, W.; Riel, H. In Comparison of VLS Grown Si NW Tunnel FETs with Different Gate Stacks. 2009 Proceedings of the European Solid State Device Research Conference, 14–18 Sep, 2009; pp 448–451.

5. Mayer, F.; Royer, C. L.; Damlencourt, J.; Romanjek, K.; Andrieu, F.; Tabone, C.; Previtali, B.; Deleonibus, S. Impact of SOI, Si1-XGexOI and GeOI Substrates on CMOS Compatible Tunnel FET Performance. 2008 IEEE International Electron Devices Meeting, 15–17 Dec, 2008; pp 1–5.

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