A New Offset Gated Poly-Si TFT Using a Wet Oxidation

Abstract

Several off-set gated TFTs have been proposed to reduce the off current. However, those structures may require an additional mask and photolithography process step. We propose a novel off-set gated poly-Si TFT which reduces the off current considerably without any additional mask.We have simulated the device characteristics by a numerical simulator in order to verify the proposed TFT. The simulation results show that the off current of the new device has been reduced to 0.ipA. The reduction of on current is much less than the off current reduction and the on/off current ratios exceeding 107 have been accomplished.