Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics

Abstract

AbstractOf the numerous requirements for advanced VLSI silicon microelectronics, power dissipation per unit area, speed, packing density and radiation hardness are especially important. Power dissipation and speed have forced an evolutionary path from PMOS to NMOS to NMOS E/D and to the currently used CMOS. As evidenced by the large number of publications, CMOS on an insulating substrate is receiving increased attention due to its potential as the next generation in MOS evolution. We review results of our previous and current research in silicon on sapphire (SOS) which has led to high quality ultrathin SOS (<100 nm thick) appropriate for high density CMOS circuitry. Basic materials developments, device performance, and CMOS design considerations in 100 nm thick improved SOS will be discussed.