Author:
Foad M. A.,Murrell A. J.,Collart E. J. H.,de Cock G.,Jennings D.,Current M. I.
Abstract
ABSTRACTAs the drive towards the production of 100 nm CMOS devices pick up speed, the practical aspect of transistor shallow junction formation, including a large menu of process integration issues, must now be solved in a short order. The most direct path to 50 nm junction depths is through the sub-keV boron implantation and rapid thermal annealing.The material aspects of the process integration centers on: (1) CMOS devices for shallow, highly-activated and abrupt junctions (involving the choice of ion species [B, BF, B10H14, BSi2, etc.], substrate materials [ Cz, Epi, SOI], anneal conditions [ramp rate, soak time, ambient gas], etc.) and (2) Defect-dopant interactions during annealing (including surface reactions of high concentration species [B, F], diffusion and carrier trapping by background and co-implanted species [C, 0, F, etc.].Process data for atomic and electrical activity profiles as well as defect and interface structures will be presented to illustrate progress towards understanding these complex process interactions. A particular focus will be the effects of anneal ambient and rapid temperature rise times approaching the “pike” anneal ideal.
Publisher
Springer Science and Business Media LLC
Cited by
12 articles.
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