High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET
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Published:2023-04-08
Issue:8
Volume:13
Page:1310
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ISSN:2079-4991
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Container-title:Nanomaterials
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language:en
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Short-container-title:Nanomaterials
Author:
Yao Yi-Ju1, Yang Ching-Ru2, Tseng Ting-Yu2, Chang Heng-Jia2, Lin Tsai-Jung2, Luo Guang-Li3, Hou Fu-Ju3, Wu Yung-Chun2, Chang-Liao Kuei-Shu2
Affiliation:
1. College of Semiconductor Research, National Tsing Hua University, Hsinchu 30013, Taiwan 2. Department of Engineering and System Science, National Tsing Hua University, Hsinchu 30013, Taiwan 3. Taiwan Semiconductor Research Institute, Hsinchu 30078, Taiwan
Abstract
This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinFET, and Si0.8Ge0.2/Si SL FinFET, were comprehensively compared with HfO2 = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si0.8Ge0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SSavg) of 88 mV/dec, the highest maximum transconductance (Gm, max) of 375.2 μS/μm, and the highest ON–OFF current ratio (ION/IOFF), approximately 106 at VOV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal–oxide–semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si0.8Ge0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.
Funder
Ministry of Science and Technology, Taiwan
Subject
General Materials Science,General Chemical Engineering
Reference19 articles.
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