Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs-Reference-Cited by-同舟云学术

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Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

Published:2018-12 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Electron Devices Meeting (IEDM)
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Author:

van Dal M.J.H.,Vellianitis G.,Doornbos G.,Duriez B.,Holland M.C.,Vasen T.,Afzalian A.,Chen E.,Su S.K.,Chen T.K.,Shen T.M.,Wu Z.Q.,Diaz C.H.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8601505/8614478/08614577.pdf?arnumber=8614577

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs;IEEE Transactions on Electron Devices;2024-01

2. Modeling the impact of incomplete conformality during atomic layer processing;Solid-State Electronics;2024-01

3. Extremely High-κ Hf_0.2Zr_0.8O₂ Gate Stacks Integrated Into Eight Stacked Ge_0.95Si_0.05 Nanowires and Nanosheets nFETs to Boost I_ON;IEEE Transactions on Electron Devices;2023-12

4. Fabrication and performance of highly stacked GeSi nanowire field effect transistors;Communications Engineering;2023-11-01

5. Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications;Scientific Reports;2023-06-09

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