Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process
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Published:2023-07-21
Issue:14
Volume:13
Page:2127
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ISSN:2079-4991
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Container-title:Nanomaterials
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language:en
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Short-container-title:Nanomaterials
Author:
Liu Enxu12, Li Junjie12ORCID, Zhou Na12, Chen Rui12, Shao Hua12, Gao Jianfeng12, Zhang Qingzhu12ORCID, Kong Zhenzhen12ORCID, Lin Hongxiao12, Zhang Chenchen1, Lai Panpan12, Yang Chaoran12, Liu Yang1, Wang Guilei34ORCID, Zhao Chao3, Yang Tao12, Yin Huaxiang12ORCID, Li Junfeng12, Luo Jun12ORCID, Wang Wenwu12
Affiliation:
1. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing 100029, China 2. Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China 3. Beijing Superstring Academy of Memory Technology, Beijing 100176, China 4. Hefei National Laboratory, Hefei 230088, China
Abstract
Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.
Funder
Strategic Priority Research Program of the Chinese Academy of Sciences Chinese Academy of Sciences Supporting Technology Talent Project Beijing Superstring Academy of Memory Technology Development of dry release function for gate-all-around (GAA) nanosheet devices Innovation Program for Quantum Science and Technology
Subject
General Materials Science,General Chemical Engineering
Reference25 articles.
1. Cramming more components onto integrated circuits;Moore;IEEE Solid-State Circuits Newsl.,1965 2. Li, J., Li, Y., Zhou, N., Xiong, W., Wang, G., Zhang, Q., Du, A., Gao, J., Kong, Z., and Lin, H. (2020). Study of silicon nitride inner spacer formation in process of gate-all-around nano-transistors. Nanomaterials, 10. 3. Sun, X., Wang, D., Qian, L., Liu, T., Yang, J., Chen, K., Wang, L., Huang, Z., Xu, M., and Wang, C. (2023). A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation. Nanomaterials, 13. 4. Loubet, N., Hook, T., Montanini, P., Yeung, C.-W., Kanakasabapathy, S., Guillom, M., Yamashita, T., Zhang, J., Miao, X., and Wang, J. (2017, January 5–8). Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. Proceedings of the 2017 Symposium on VLSI Technology, Kyoto, Japan. 5. Wang, Y., Chen, Z., Wang, C., Keller, N., Antonelli, G.A., Liu, Z., Ribaudo, T., and Grynko, R. (2023, January 1–4). 3D NAND Oxide/Nitride Tier Stack Thickness Measurements with Infrared Metrology. Proceedings of the 2023 34th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA.
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