Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET-Reference-Cited by-同舟云学术

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Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET

Published:2024-04-09 Issue: Volume: Page:23
ISSN:
Container-title:Advanced Etch Technology and Process Integration for Nanopatterning XIII
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Author:

Liu Enxu,Yang Chaoran,Li Junjie,Zhou Na,Xia Longrui,Chen Rui,Shao Hua,Gao Jianfeng,Kong Zhenzhen,Zhang Chenchen,Lai Panpan,Yang Tao,Wei Yayi,Li Junfeng,Luo Jun,Wang Wenwu

Publisher

SPIE

Reference7 articles.

1. A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around Nanosheet Devices;Loubet,2019

2. Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET;Loubet,2017

3. A Review of the Gate-All-Around Nanosheet FET Process Opportunities

4. Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

5. A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

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