Affiliation:
1. School of Microelectronics, Xidian University, Xi’an 710126, China
2. Guangzhou Institute of Technology, Xidian University, Guangzhou 510555, China
3. Technology on Reliability Physics and Application Technology of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China
Abstract
Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip (SoC) communication design. Application mapping is the first and most important step in the NoC synthesis flow, which determines most of the NoC design performance. NoC mapping has been confirmed as an NP-hard (Non-Polynomial hard) problem, which could not be solved in polynomial time. Various heuristic mapping algorithms have been applied to the mapping problem. However, the heuristic algorithm easily falls into a local optimal solution which causes performance loss. Additionally, regular topologies of NoC, such as the ring, torus, etc., may generate symmetric solutions in the NoC mapping process, which increase the performance loss. Machine learning involves data-driven methods to analyze trends, find relationships, and develop models to predict things based on datasets. In this paper, an NoC machine learning mapping algorithm is proposed to solve a mapping problem. A Low-complexity and no symmetry NoC mapping dataset is defined, and a data augmentation approach is proposed to build dataset. With the dataset defined, a multi-label machine learning is established. The simulation results have confirmed that the machine learning mapping algorithm is proposed have at least 99.6% model accuracy and an average of 96.3% mapping accuracy.
Funder
Natural Science Foundation of Guangdong, China
Subject
Physics and Astronomy (miscellaneous),General Mathematics,Chemistry (miscellaneous),Computer Science (miscellaneous)
Reference32 articles.
1. Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores;Soumya;J. Syst. Archit.,2014
2. Dally, W.J., and Towles, B. (2001, January 22). Route packets, not wires: On-chip interconnection networks. Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), Las Vegas, NV, USA.
3. An Analytical Approach for Network-on-Chip Performance Analysis;Ogras;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2010
4. Congestion-aware ant colony based routing algorithms for efficient application execution on Network-on-Chip platform;Nedjah;Expert Syst. Appl.,2013
5. Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization;Sahu;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2013
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Asynchronous Circular Buffers based on FIFO for Network on Chips;2023 International Conference on Circuit Power and Computing Technologies (ICCPCT);2023-08-10