Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

Abstract

In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.