Affiliation:
1. Institute of Systems Engineering and Collaborative Laboratory for Intelligent Science and Systems, Macau University of Science and Technology, Macao 999078, China
2. State Key Laboratory of Precision Electronic Manufacturing Technology and Equipment, Guangdong University of Technology, Guangzhou 510006, China
3. IKAS Industries Technology (Suzhou) Company Ltd., Suzhou 215000, China
Abstract
Cluster tools are the key equipment in semiconductor manufacturing systems. They have been widely adopted for many wafer fabrication processes, such as chemical and physical vapor deposition processes. Reentrant wafer flows are commonly seen in cluster tool operations for deposition processes. It is very complicated to schedule cluster tools with reentrant processes. For a dual-arm cluster tool with two-time reentering, the existing studies point out that a one-wafer periodical (1-WP) schedule can be found, and it is optimal in terms of productivity. However, for some wafer fabrication processes, wafers should be processed at some PMs more than two times. This gives rise to a question of whether there still exists a 1-WP schedule for dual-arm cluster tools with the number of reentering times being more than two such that the cycle time of a tool can reach the lower bound. This problem is still open, and this is what this work wants to tackle. For a dual-arm cluster tool with the number of reentering times being k (>2) times, if there does not exist a value f ∈ {1, 2 …} such that k = 3f, theoretical proofs are given to show that a 1-WP schedule can be found, otherwise it does not exist. For cases with a 1-WP schedule, the cycle time can be obtained by analytical expressions. For the cases without a 1-WP schedule, two new methods for a three-wafer periodical schedule are proposed to improve the system productivity by comparing it with an existing three-wafer periodical schedule. The applications of the obtained results are demonstrated by examples. Wafer residency time constraints are required for some wafer fabrication processes. Note that the results obtained in this work cannot be directly applied to cluster tools with both reentrant wafer flows and wafer residency time constraints. Nevertheless, schedulablity and scheduling analyses for that applications can be conducted based on the obtained results in this work.
Funder
Science and Technology Development Fund
Macau SAR
Research Fund of Guangdong-Hong Kong-Macao Joint Laboratory for Intelligent Micro-Nano Optoelectronic Technology
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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