Low Cost Test Pattern Generation in Scan-Based BIST Schemes
-
Published:2019-03-12
Issue:3
Volume:8
Page:314
-
ISSN:2079-9292
-
Container-title:Electronics
-
language:en
-
Short-container-title:Electronics
Author:
Zhang Guohe,Yuan Ye,Liang Feng,Wei Sufen,Yang Cheng-Fu
Abstract
This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.
Funder
The Core Electronic Devices, High-end General Chips and Basic Software Products Projects of China
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference21 articles.
1. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits;Bushnell,2013
2. VLSI Testing;Lei,2008
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献