Affiliation:
1. 3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332, USA
2. Department of Electrical Engineering, Pennsylvania State University, University Park, PA 16802, USA
Abstract
The ever-increasing demand for faster computing has led us to an era of heterogeneous integration, where interposers and package substrates have become essential components for further performance scaling. High-bandwidth connections are needed for faster communication between logic and memory dies. There are several limitations to current generation technologies, and dielectric buildup layers are a key part of addressing those issues. Although there are several polymer dielectrics available commercially, there are numerous challenges associated with incorporating them into interposers or package substrates. This article reviewed the properties of polymer dielectric materials currently available, their properties, and the challenges associated with their fabrication, electrical performance, mechanical reliability, and electrical reliability. The current state-of-the-art is discussed, and guidelines are provided for polymer dielectrics for the next-generation interposers.
Funder
3D Systems Packaging Research Center, Georgia Institute of Technology
Subject
Polymers and Plastics,General Chemistry
Reference78 articles.
1. Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect;Mahajan;IEEE Trans. Compon. Packag. Manuf. Technol.,2019
2. Oi, K., Otake, S., Shimizu, N., Watanabe, S., Kunimoto, Y., Kurihara, T., Koyama, T., Tanaka, M., Aryasomayajula, L., and Kutlu, Z. (2014, January 27–30). Development of new 2.5 D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps. Proceedings of the 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, USA.
3. Yamada, T. (2015, January 22–25). Organic Interposer and Embedded Substrate. Proceedings of the 2015 Packaging Symposium, Braşov, Romania.
4. Wafer-level integration of an advanced logic-memory system through the second-generation CoWoS technology;Hou;IEEE Trans. Electron Devices,2017
5. Analysis on signal and power integrity of 2.3 D structure organic package;Tsukamoto;Int. Symp. Microelectron.,2019
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