P-channel logic 2 T eDRAM macro with high retention bit architecture-Reference-Cited by-同舟云学术

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P-channel logic 2 T eDRAM macro with high retention bit architecture

Published:2018-05-29 Issue:7 Volume:46 Page:1416-1425
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int J Circ Theor Appl

Author:

Manisankar Sivasundar¹,Chung Yeonbae¹^ORCID

Affiliation:

1. School of Electronics Engineering; Kyungpook National University; Daegu Republic of Korea

Funder

Kyungpook National University Bokhyeon Research Fund, 2016

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. A novel dynamic memory cell with internal voltage gain;Luk;IEEE J Solid State Circuits,2005

2. A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches;Chun;IEEE J Solid State Circuits,2011

3. A 2T1C embedded DRAM macro with no boosted supplies featuring a 7T SRAM based repair and a cell storage monitor;Chun;IEEE J Solid State Circuits,2012

4. A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode;Zhang;IEEE Trans Circuits Syst I: Regul Pap,2013

5. Low-power high-throughput LDPC decoder using non-refresh embedded DRAM;Park;IEEE J Solid State Circuits,2014

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications;International Journal of Circuit Theory and Applications;2021-11

2. Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage;Journal of Nanoscience and Nanotechnology;2020-11-01

3. Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems;Japanese Journal of Applied Physics;2020-01-31

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