Characterization of Packaging‐Induced Stress Distributions for Small‐Scale Silicon Chips
Author:
Affiliation:
1. Manufacturing & Engineering Center, RICOH Electronic Devices. Co., Ltd. 30‐1, Saho, Kato‐shi Hyogo 673‐1447 Japan
2. Innovation R&D Division, Ricoh Campany 13‐1 Himemuro‐cho, Ikeda‐shi, Osaka 563‐8501 Japan
Publisher
Wiley
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/tee.23187
Reference12 articles.
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5. Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance
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