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A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

  • Published:2021-02-26 Issue:7 Volume:49 Page:2199-2213
  • ISSN:0098-9886
  • Container-title:International Journal of Circuit Theory and Applications
  • language:en
  • Short-container-title:Int J Circ Theor Appl

Author:

Ghasemi Mir Majid1,Fathi Amir1ORCID,Mousazadeh Morteza1,Khoei Abdollah1

Affiliation:

1. Microelectronics Research Laboratory Urmia University Urmia 57159 Iran

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Low power Wallace multiplier design based on wide counters

2. Circuit techniques for CMOS low-power high-performance multipliers

3. Waser S.andFlynn M. J. Introduction to arithmetic for digital systems designers 1982.

4. Omondi A. R. Computer arithmetic systems algorithms architecture and implementation 1994.

5. Simplified carry save adder-based array multiplier scheme and circuits design

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1. Optimized Design of Power Efficient FIR Filter Using Modified Booth Multiplier;2021 4th International Conference on Recent Trends in Computer Science and Technology (ICRTCST);2022-02-11

2. Design and performance analysis of an ultra‐high‐speed 5‐2 compressor;International Journal of Circuit Theory and Applications;2022-02-09

3. High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA;International Journal of Circuit Theory and Applications;2021-08-26

4. Design and Implementation of Low power FinFET based Compressor;2021 3rd International Conference on Signal Processing and Communication (ICPSC);2021-05-13

5. A three‐stage stochastic planning model for enhancing the resilience of distribution systems with microgrid formation strategy;IET Generation, Transmission & Distribution;2021-02-26
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