Simplified carry save adder-based array multiplier scheme and circuits design-Reference-Cited by-同舟云学术

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Simplified carry save adder-based array multiplier scheme and circuits design

Published:2014-05-01 Issue:9 Volume:43 Page:1226-1234
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Jia Song¹,Lyu Shigong¹,Li Xiayu¹,Liu Li¹,He Yandong¹

Affiliation:

1. Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics; Peking University; 100871 Beijing China

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cta.1998/fullpdf

Reference17 articles.

1. Low power Wallace multiplier design based on wide counters;Abed;International Journal of Circuit Theory and Applications,2012

2. A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters;Meher;IEEE Transactions on Very Large Scale Integration Systems (VLSI),2011

3. Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers;Tu;IEEE Transactions on Computers,2009

4. Asynchronous cross-pipelined multiplier;Butas;IEEE Journal of Solid-State Circuits,2011

5. A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified Booth algorithm;Seo;IEEE Transactions on Very Large Scale Integration Systems (VLSI),2010

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier;International Journal of Circuit Theory and Applications;2021-02-26

2. Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers;International Journal of Circuit Theory and Applications;2021-01-27

3. Fast Large Integer Modular Addition in GF(p) Using Novel Attribute-Based Representation;IEEE Access;2019

4. Double-precision Dual Mode Logic carry-save multiplier;Integration;2019-01

5. Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders;Microelectronics Journal;2015-09

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