Complete delay modeling of sub-threshold CMOS logic gates for low-power application
Author:
Affiliation:
1. Electronics and Telecommunication Engineering Department; Jadavpur University; Kolkata India
2. Nano Lab; IISC; Bangalore India
Publisher
Wiley
Subject
Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation
Link
http://onlinelibrary.wiley.com/wol1/doi/10.1002/jnm.2053/fullpdf
Reference21 articles.
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2. Nanopower subthreshold MCML in submicrometer CMOS technology;Cannillo;IEEE Trans Circuit Syst-I,2009
3. Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective;Gupta;IEEE Proc,2010
4. Flexible circuits and architectures for ultralow power, pp. 267-282;Calhoun;IEEE Proc,2010
5. A 180-mV subthreshold FFT processor using a minimum energy design methodology;Wang;IEEE JSSC,2005
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