An approach for modeling propagation delay of a subthreshold inverter incorporating DIBL effect
Author:
Affiliation:
1. Netaji Subhash Engineering College,Dept.of Electronics and ommunication Engineering,Kolkata,India
2. University of Calcutta,Institute of Radiophysics and Electronic,Kolkata,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10134754/10134560/10134823.pdf?arnumber=10134823
Reference19 articles.
1. VLSI limitations from drain-induced barrier lowering
2. Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective
3. Compact Modeling of Nonlinear Contact Effects in Short-Channel Coplanar and Staggered Organic Thin-Film Transistors
4. A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control
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1. Power and Delay Analysis of a CMOS Inverter;2023 International Conference on Data Science and Network Security (ICDSNS);2023-07-28
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