Investigation of long channel bulk <scp>MOSFETs</scp> threshold voltage model down to 10 <scp>mK</scp> and key analog parameters at 4 K-Reference-Cited by-同舟云学术

Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K

Published:2024-05 Issue:3 Volume:37 Page:
ISSN:0894-3370
Container-title:International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
language:en
Short-container-title:Int J Numerical Modelling

Author:

Su Hao¹^ORCID,Cai Yiyuan¹,Lin Yuhuan¹,Xie Yunfeng¹,Mai Yongfeng²,Zhou Shenghua²³,Hu Guangchong³,He Yu²³,Zhou Feichi¹,Liu Xiaoguang¹,Lin Longyang¹,Li Yida¹,Yu Hongyu¹,Chen Kai¹

Affiliation:

1. School of Microelectronics Southern University of Science and Technology Shenzhen China

2. Southern University of Science and Technology Shenzhen China

3. International Quantum Academy Shenzhen China

Abstract

AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) and gm/IDS related parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.

Funder

National Natural Science Foundation of China

Basic and Applied Basic Research Foundation of Guangdong Province

Publisher

Wiley

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/jnm.3258

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