Characterization and Modeling of Mismatch in Cryo-CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology
Link
http://xplorestaging.ieee.org/ielx7/6245494/8949832/09015956.pdf?arnumber=9015956
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1. Cryogenic-Aware Forward Body Biasing in Bulk CMOS;IEEE Electron Device Letters;2024-02
2. Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications;Chip;2023-12
3. A Polar-Modulation-Based Cryogenic Transmon Qubit State Controller in 28 nm Bulk CMOS for Superconducting Quantum Computing;IEEE Journal of Solid-State Circuits;2023-11
4. Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell;IEEE Journal of Solid-State Circuits;2023-11
5. A 400uW 3.6GHz-4.6GHz Low Power Cryogenic CP-PLL with Transformer-Based VCO in 28nm Bulk CMOS;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27
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