Yield-aware sizing of pipeline ADC using a multiple-objective evolutionary algorithm

Author:

Mirzaie Nahid12,Shamsi Hossein1,Byun Gyung-Su2

Affiliation:

1. Faculty of Electrical Engineering; K. N. Toosi University of Technology; Tehran Iran

2. Lyle Department of Electrical Engineering; Southern Methodist University; Dallas TX USA

Funder

National Sleep Foundation

NSF CAREER

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference44 articles.

1. A survey of yield modeling and yield enhancement methods;Milor;IEEE Transactions Semiconductor Manufacturing,2013

2. A 10-b 1-GHz 33-mW CMOS ADC. IEEE journal solid-state circuits;Sahoo;IEEE Journal of Solid-State Circuits,2013

3. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies

4. The parametric yield enhancement of integrated circuits;Singha;International Journal of Circuit Theory and Applications,1991

5. An INL yield model of the digital-to-analog converter;Park;IEEE Transactions Circuits System. I,2013

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