FFT-based calibration method for 1.5 bit/stage pipelined ADCs

Author:

Lee Shuenn-Yuh1,Liang Ming-Chun1,Hsieh Cheng-Han1

Affiliation:

1. Department of Electrical Engineering; National Cheng Kung University; No. 1, University Rd. Tainan Taiwan, R.O.C.

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. A 10b 25MS/s 4.8mW 0.13μm CMOS ADC with switched-bias power-reduction techniques;Choi;International Journal of Circuit Theory and Applications,2009

2. A design example of a 65nm CMOS operational amplifier;Schlogl;International Journal of Circuit Theory and Applications,Jan. 2007

3. Background calibration with piecewise linearized error model for CMOS pipeline A/D converter;Yuan;IEEE Transactions on Circuits and Systems I: Regular Papers,2008

4. A 12-Bit 200-MHz CMOS ADC;Sahoo;IEEE Journal Solid-State Circuits,2009

5. Background calibration techniques for multistage pipelined ADCs with digital redundancy;Li;IEEE Transactions on Circuits and Systems II: ANalog and Digital Signal Processing,2003

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