Multiplier-less VLSI architectures for radix-22folded pipelined complex FFT core-Reference-Cited by-同舟云学术

Multiplier-less VLSI architectures for radix-22folded pipelined complex FFT core

Author:

Mankar Abhishek¹,Prasad N²^ORCID,Das Ansuman DiptiSankar³,Meher Sukadev⁴

Affiliation:

1. Department of Electronics and Communication Engineering; IEC Group of Institutions; Greater Noida India

2. Department of Electronics and Electrical Communication Engineering; Indian Institute of Technology; Kharagpur 721302 India

3. IBM India Private Ltd.; Hyderabad India

4. Department of Electronics and Communication Engineering; National Institute of Technology; Rourkela 769008 India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. A 2.4-GS/s FFT processor for OFDM-based WPAN applications;Tang;IEEE Transactions on Circuits and Systems I: Regular Papers,2010

2. A pipelined FFT architecture for real-valued signals;Garrido;IEEE Transactions on Circuits and Systems I: Regular Papers,2009

4. FFT-based calibration method for 1.5 bit/stage pipelined ADCs;Lee;International Journal of Circuit Theory and Applications,2013

5. Fast computation of the discrete Hartley transform;Jain;International Journal of Circuit Theory and Applications,2010

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3. Performance analysis of improved dynamic kernel function in fast Fourier transform;2019 14th IEEE International Conference on Electronic Measurement & Instruments (ICEMI);2019-11