Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET
Author:
Affiliation:
1. Department of Electronics and Communication Engineering Malaviya National Institute of Technology Jaipur Rajasthan India
2. Department of Electronics and Communication Engineering National Institute of Technology Silchar Silchar Assam India
Funder
Science and Engineering Research Board
Publisher
Wiley
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/mmce.22704
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1. Device scaling limits of Si MOSFETs and their application dependencies
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5. Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic
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