Optimal integrated code generation for VLIW architectures-Reference-Cited by-同舟云学术

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Optimal integrated code generation for VLIW architectures

Published:2006 Issue:11 Volume:18 Page:1353-1390
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Kessler Christoph,Bednarski Andrzej

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference58 articles.

1. Code Optimization Techniques for Embedded Processors. Kluwer: Dordrecht, 2000.

2. Texas Instruments. TMS320C6000 CPU and Instruction Set Reference Guide. Texas Instruments: Dallas, TX, 2000.

3. ARM Ltd. ARM9E-S™. Technical Reference Manual ARM DDI0240A, Rev. 2, May 2002.

4. Register allocation via coloring

5. Code Generation for Expressions with Common Subexpressions

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1. Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming;ACM Transactions on Design Automation of Electronic Systems;2024-09-04

2. Speedup the optimization of maximal closure of a node-weighted directed acyclic graph;OPSEARCH;2022-07-08

3. Survey on Combinatorial Register Allocation and Instruction Scheduling;ACM Computing Surveys;2020-05-31

4. Combinatorial Register Allocation and Instruction Scheduling;ACM Transactions on Programming Languages and Systems;2019-09-30

5. Compiling for VLIW DSPs;Handbook of Signal Processing Systems;2018-10-14

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