AXC: A new format to perform the SpMV oriented to Intel Xeon Phi architecture in OpenCL-Reference-Cited by-同舟云学术

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AXC: A new format to perform the SpMV oriented to Intel Xeon Phi architecture in OpenCL

Published:2018-07-31 Issue:1 Volume:31 Page:e4864
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Coronado-Barrientos E.¹^ORCID,Indalecio G.¹,García-Loureiro A.¹

Affiliation:

1. Centro Singular de Investigación en Tecnoloxías da Información (CiTIUS); Universidade de Santiago de Compostela; Santiago de Compostela Spain

Funder

FEDER funds and Xunta de Galicia

Spanish Government (MCYT)

Ministerio de Ciencia y Tecnología

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cpe.4864/fullpdf

Reference36 articles.

1. Study of parallel numerical methods for semiconductor device simulation;Seoane;Int J Numer Model Electron Netw Devices Fields,2006

2. Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods

3. Iterative Methods for Sparse Linear Systems

4. Bell N Garland M Efficient Sparse Matrix-Vector Multiplication on CUDA Santa Clara, CA NVIDIA 2008

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation and optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format;Scientific Reports;2024-07-17

2. Adaptive Hybrid Storage Format for Sparse Matrix–Vector Multiplication on Multi-Core SIMD CPUs;Applied Sciences;2022-09-29

3. A simple and efficient storage format for SIMD-accelerated SpMV;Cluster Computing;2021-06-20

4. A new AXT format for an efficient SpMV product using AVX-512 instructions and CUDA;Advances in Engineering Software;2021-06

5. tpSpMV: A two-phase large-scale sparse matrix-vector multiplication kernel for manycore architectures;Information Sciences;2020-06

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