tpSpMV: A two-phase large-scale sparse matrix-vector multiplication kernel for manycore architectures-Reference-Cited by-同舟云学术

tpSpMV: A two-phase large-scale sparse matrix-vector multiplication kernel for manycore architectures

Published:2020-06 Issue: Volume:523 Page:279-295
ISSN:0020-0255
Container-title:Information Sciences
language:en
Short-container-title:Information Sciences

Author:

Chen Yuedan^ORCID,Xiao Guoqing^ORCID,Wu Fan,Tang Zhuo,Li Keqin^ORCID

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Artificial Intelligence,Information Systems and Management,Computer Science Applications,Theoretical Computer Science,Control and Systems Engineering,Software

Reference34 articles.

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2. Accelerating SPMV on FPGAs by compressing nonzero values;Grigoras,2015

3. CVR: efficient vectorization of SPMV on x86 processors;Xie,2018

4. AXC: a new format to perform the SPMV oriented to intel xeon phi architecture in opencl;Coronado-Barrientos;Concurr. Comput.,2019

5. Towards efficient SPMV on sunway manycore architectures;Liu,2018

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3. Optimization of Large-Scale Sparse Matrix-Vector Multiplication on Multi-GPU Systems;ACM Transactions on Architecture and Code Optimization;2024-07-08

4. Block-wise dynamic mixed-precision for sparse matrix-vector multiplication on GPUs;The Journal of Supercomputing;2024-03-11

5. A Survey of Accelerating Parallel Sparse Linear Algebra;ACM Computing Surveys;2023-08-28