Three dimensional simulation of short channel effects in junction less FinFETs-Reference-Cited by-同舟云学术

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Three dimensional simulation of short channel effects in junction less FinFETs

Published:2021-11-23 Issue: Volume: Page:
ISSN:2577-8196
Container-title:Engineering Reports
language:en
Short-container-title:Engineering Reports

Author:

Hosseini Seyed Akram¹²,Eskandarian Abdollah²^ORCID,ghadimi Abbas³

Affiliation:

1. Department of Electrical Engineering Guilan Science and Research Branch, Islamic Azad University Rasht Iran

2. Department of Electrical Engineering, Rasht Branch Islamic Azad University Rasht Iran

3. Department of Electrical Engineering, Lahijan Branch Islamic Azad University Lahijan Iran

Funder

Islamic Azad University

Publisher

Wiley

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/eng2.12481

Reference35 articles.

1. Nanowire transistors without junctions

2. Junctionless Nanowire Transistor (JNT): Properties and design guidelines

3. Simulation of junctionless Si nanowire transistors with 3 nm gate length

4. Performance estimation of junctionless multigate transistors

5. Investigation of high-performance sub-50nm junctionless nanowire transistors

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Hysteresis Curve on Subthreshold Swing in Ferroelectric FET;Vietnam Journal of Science and Technology;2024-02-23

2. A FinFET-based low-power, stable 8T SRAM cell with high yield;AEU - International Journal of Electronics and Communications;2024-02

3. A review on effect of various high-k dielectric materials on the performance of FinFET device;Materials Today: Proceedings;2023

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