A Comparative Study on Self‐Aligned Top‐Gate Thin‐Film Transistors with Silicon Nitride as the Interlayer

Abstract

Thin‐film transistors (TFTs) with self‐aligned top‐gate structure are fabricated, in which the source/drain region is pretreated to be highly conductive during the deposition of silicon nitride as the interlayer. Without deteriorating the properties of the device's channel layer, the basic performance of TFTs can be simply controlled by altering the SiH4 flow rate during the deposition of silicon nitride film. Furthermore, the diffusion of hydrogen dissociated from SiH4 precursor, which can passivate the electron traps at the interface between the channel and dielectric layer or in the bulk of the dielectric layer, can significantly improve the positive bias temperature stress stability. The charge trapping mechanism is verified using the stretched‐exponential model, and the rising values of the fitting parameters (ΔVth0 and τ) show that the TFTs stability improves as the flow rate of SiH4 rises. This approach can reduce the cost and simplify the manufacturing of thin‐film transistors.