FinFET 4T‐SRAM operable at near‐threshold region
Author:
Affiliation:
1. Graduate School of EngineeringGifu University Japan
2. Department of Electrical, Electronic, and Computer Engineering, Faculty of EngineeringGifu University Japan
Publisher
Wiley
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy,Signal Processing
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/ecj.12162
Reference14 articles.
1. A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
2. SinhaS YericG ChandraV ClineB CaoY Exploring sub‐20 nm FinFET design with predictive technology models. Proc. IEEE DAC Design Automation Conference San Francisco CA 2012:283‐288.
3. WangA CalhounBH ChandrakasanAP A 256kb sub‐threshold SRAM in 65nm CMOS. Proc. IEEE Solid‐State Circuits Conference San Francisco CA 2006:480‐481.
4. Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
5. YabuuchiM MorimotoM TsukamotoY et al.16 nm FinFET high‐k/metal‐gate 256‐kbit 6T SRAM macros with wordline overdriven assist. Proc. IEEE International Electron Devices Meeting San Francisco CA 2014:3.3.1‐3.3.3.
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1. FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm;Analog Integrated Circuits and Signal Processing;2022-05-31
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