A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements-Reference-Cited by-同舟云学术

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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Published:2012-01 Issue:1 Volume:47 Page:97-106
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Pilo Harold,Arsovski Igor,Batson Kevin,Braceras Geordie,Gabric John,Houle Robert,Lamphier Steve,Radens Carl,Seferagic Adnan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6109882/06033050.pdf?arnumber=6033050

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-01

3. Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories;Journal of Low Power Electronics and Applications;2021-09-24

4. A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02

5. Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM;IEEE Access;2021

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