Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits-Reference-Cited by-同舟云学术

Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits

Published:2020-11-17 Issue:3 Volume:34 Page:
ISSN:0894-3370
Container-title:International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
language:en
Short-container-title:Int J Numer Model

Author:

Hu Qing‐Hao¹,Zhao Wen‐Sheng¹^ORCID,Fu Kai¹,Wang Da‐Wei¹²,Wang Gaofeng¹

Affiliation:

1. MOE Engineering Research Center of Smart Microsensors and Microsystems, School of Electronics and Information Hangzhou Dianzi University Hangzhou China

2. Zhejiang Provincial Key Laboratory of Advanced Microelectronic Intelligent Systems and Applications Hangzhou China

Funder

National Natural Science Foundation of China

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/jnm.2842

Reference36 articles.

1. Voltage optimization of power delivery networks through power bump and TSV placement in 3D ICs;Son SN;ETRI J,2014

2. High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

3. Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

4. Transient Analysis of Through-Silicon Vias in Floating Silicon Substrate

5. Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

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