FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic-Reference-Cited by-同舟云学术

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FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Published:2020-05-16 Issue:8 Volume:48 Page:1304-1318
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int J Circ Theor Appl

Author:

Subannan Palanisamy Kesavan¹^ORCID,Ramachandran Rajeswari²

Affiliation:

1. Nandha College of Technology Erode India

2. Government College of Technology Coimbatore Tamil Nadu India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cta.2794

Reference45 articles.

1. UniyalA NiranjanV 2017 ‘A new 16‐bit ALU using variable stage adder and PTL mux’ International Conference on Computing Communication and Automation (ICCCA) pp.1374–1378.

2. ChowdhurySD ChaudhuriRR SarkarM 2017 ‘Design of 1‐bit full adder using NMOS based negative differential resistance’ Devices for Integrated Circuit (DevIC) pp.630–636.

3. KatreepalliR HaniotakisT 2017a ‘Power‐delay‐area efficient design of vedic multiplier using adaptable manchester carry chain adder’ International Conference on Communication and Signal Processing (ICCSP) pp.1418–1422.

4. RiazMH AhmedSA JavaidQ KamalT 2018 ‘Low power 4 × 4 bit multiplier design using dadda algorithm and optimized full adder’ 15th International Bhurban Conference on Applied Sciences and Technology (IBCAST) pp.392–396.

5. GadekarM ChavanR MatkarN JagushteS JoshiS 2017 ‘Design of 16T full adder circuit using 6TXNOR gates’ International Conference on Advances in Computing Communication and Control (ICAC3) pp.1–4.

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1. Revolutionizing Semiconductor Technology: A Comprehensive Review of FinFET;2024 International Conference on Communication, Computer Sciences and Engineering (IC3SE);2024-05-09

2. Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications;Journal of Electrical and Computer Engineering;2023-06-07

3. Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies;Integration;2023-01

4. Design and Implementation of ALU Using Graphene Nanoribbon Field-Effect Transistor and Fin Field-Effect Transistor;Journal of Nanomaterials;2022-07-01

5. SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits;International Journal of Circuit Theory and Applications;2022-02-16

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