Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder-Reference-Cited by-同舟云学术

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Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder

Published:2018-01 Issue: Volume: Page:
ISSN:
Container-title:2018 15th International Bhurban Conference on Applied Sciences and Technology (IBCAST)
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Author:

Riaz Muhammad Hussnain,Ahmed Syed Adrees,Javaid Qasim,Kamal Tariq

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8305560/8312171/08312254.pdf?arnumber=8312254

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Enhancing the Efficiency of Wallace Tree Multipliers Through Optimized ECSLA Design;2023 2nd International Conference on Futuristic Technologies (INCOFT);2023-11-24

2. A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03

3. Design and Implementation of a High-Performance 4-bit Vedic Multiplier Using a Novel 5-bit Adder in 90nm Technology;2022 10th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO);2022-10-13

4. FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic;International Journal of Circuit Theory and Applications;2020-05-16

5. An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm;SN Applied Sciences;2019-10-08

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