Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications
Author:
Affiliation:
1. Semiconductor Devices and VLSI Technology (SDVT) Group, Department of Electronics & Computer Engineering (E & CE), Indian Insititue of Technology (IIT), Roorkee, Roorkee-247667, Uttarakhand, India
Abstract
Publisher
Hindawi Limited
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture
Link
http://downloads.hindawi.com/archive/2009/283702.pdf
Reference25 articles.
1. Low-power CMOS digital design
2. Ultra-low-power DLMS adaptive filter for hearing aid applications
3. A 180-mV subthreshold FFT processor using a minimum energy design methodology
4. Device Optimization for Digital Subthreshold Logic Operation
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